Electrical Engineer, SerDes & Signal Integrity

Who we are

Arena Physica is on a mission to accelerate hardware innovation that powers human progress. Our name is inspired by Theodore Roosevelt's 'Citizenship in a Republic' speech. To us, entering the Arena means committing fully and accepting the risk of failure in pursuit of an audacious, worthy cause. We believe the future belongs to those brave enough to build it.

Our team of 80 combines AI engineering and applied physics expertise with deep experience in enterprise deployments. We're headquartered in NYC with presences in San Francisco and Los Angeles, backed by ~$90M from Initialized, Founders Fund, Goldcrest Capital, Fifth Down Capital, and Shield Capital.

If you're ready to do the most important work of your career, join us in the Arena.

What we do

At Arena Physica, we're building electromagnetic superintelligence. Our AI platform Atlas operationalizes physics-grounded intelligence to verify, debug, and optimize hardware across its lifecycle. Atlas is already trusted globally by the world's most advanced hardware companies, including AMD, Anduril, and Bausch & Lomb, for applications across R&D, integration testing, production assembly, and field repair.

About the role

As an Electrical Engineer specializing in SerDes and Signal Integrity, you will advance Atlas's ability to simulate, validate, and optimize high-speed digital interconnect — package breakout through PCB, connectors, and cables — for next-generation SerDes channels. You'll work at the intersection of our applied research team building the first EM Foundation Model and our engineering teams operationalizing that intelligence for customer hardware design and verification workflows.

How you will contribute

• Model SerDes channels end-to-end
  • Simulate high-speed digital interconnect — PCB traces, vias, connectors, packages, cables — from transmitter to receiver.
  • Generate S-parameters, RLGC, and channel operating margin (COM) estimates for PAM4 links at 112G and 224G and higher (e.g., 448 PAM 6)
• Characterize signal integrity risk
  • Quantify insertion/return loss, crosstalk (NEXT/FEXT), impedance discontinuities, via stub resonance, skew and mode conversion, dielectric/roughness loss, and dispersion against each link's loss budget.
  • Identify backdrill depth, antipad, and ground-via stitching changes that close a margin gap.
• Build EM simulation capabilities for Atlas
  • Develop and maintain production-grade 2.5D/3D EM simulation workflows for SerDes-relevant structures: via transitions, differential breakouts, connector launches, package solder balls.
  • Ensure outputs are repeatable, automatable, and production-grade.
• Bring PCB design expertise
  • Work in Altium or Cadence OrCAD on stackup, routing, and via design for controlled-impedance, low-skew differential channels.
  • Support integration of that expertise into Atlas's design workflows.
• Validate against lab measurement
  • Correlate simulation with VNA, TDR, and BER lab measurement.
  • Define acceptance criteria for channel margin and drive root-cause analysis when simulated and measured results disagree.
• Automate expert workflows
  • Convert SerDes-specific best practices such as de-embedding, port definition, backdrill depth selection, antipad/stub optimization into repeatable, parameterized simulation pipelines.

Qualifications

• 3+ years of professional industry experience in signal integrity, SerDes channel engineering, or high-speed digital design at a leading hardware or semiconductor company.
• Strong grounding in SI fundamentals: insertion/return loss, crosstalk, impedance discontinuities, via stub resonance and backdrilling, skew/mode conversion, dielectric and conductor loss, de-embedding.
• Practical proficiency with 2.5D/3D EM solvers (e.g., Ansys HFSS/SIwave, Keysight ADS/Momentum, Cadence Sigrity/Clarity) and high-speed channel simulation for S-parameters, RLGC extraction, and channel operating margin (COM) analysis.
• Working knowledge of high-speed SerDes standards, including 112G/224G PAM4 (IEEE 802.3ck/dj, OIF-CEI-112G/224G) and PCIe Gen5/6, and experience using IBIS-AMI models for link-level analysis, eye-diagram optimization, and BER budgeting.
• Lab proficiency with high-speed measurement equipment (VNA, TDR, and BERT), including authoring test plans and correlating empirical measurements back to simulation models.
• PCB design experience in Altium or Cadence OrCAD/Allegro, specifically stackup definition and routing for impedance-controlled differential channels.
• Python proficiency for scripting simulation pipelines and post-processing.
• [Preferred] PhD in Electrical Engineering, Applied Physics, or a related field.
• [Preferred] Experience with low-loss laminate material systems and high-volume PCB manufacturing constraints.
• [Preferred] Experience debugging EMI/EMC de-sense issues on high-speed digital boards.
• Work in person at Arena Physica's NYC HQ when not traveling
• Travel domestically and internationally (up to 25% of your time)

Benefits & Perks Include:

• 100% of the monthly premiums covered with Aetna medical vision, and dental insurance for you and your dependents
• 401(k) Retirement Plan
• Unlimited PTO
• Lunch every day from local restaurants via Sharebite
• Relocation support provided

The base salary range for this position is $150,000 - $250,000 yr. However, base pay offered may vary depending on job-related knowledge, skills, and experience. In addition to base salary, we also offer competitive equity and benefits packages.

This position may require access to information protected under U.S. export control laws and regulations, including the Export Administration Regulations (EAR) and the International Traffic in Arms Regulations (ITAR). Please note that any offer for employment may be conditioned on authorization to receive software or technology controlled under these U.S. export control laws and regulations without sponsorship for an export license.